74ALS74A

INTEGRATED CIRCUITS 74ALS74A Dual D-type flip-flop with set and reset Product specification IC05 Data Handbook 1996 Jul 01 Philips Semiconductors Philips Semiconductors Product specification Dual D-type flip-flop with set and reset 74ALS74A DESCRIPTION The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset are inactive (High), data at the D input is transferred to the Q and Q outputs on the Low-to-High transition of the clock. Data must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. TYPICAL SUPPLY CURRENT (TOTAL) 3.0mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS74AN 74ALS74AD 74ALS74ADB DRAWING NUMBER SOT27-1 SOT108-1 SOT337-1 14-pin plastic DIP 14-pin plastic SO 14-pin plastic SSOP Type II PIN CONFIGURATION RD0 D0 CP0 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1 TYPE 74ALS74A TYPICAL fMAX 150MHz SD0 Q0 Q0 GND SF00045 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0, D1 CP0, CP1...