74AHCT74

INTEGRATED CIRCUITS DATA SHEET 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1999 Aug 05 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Balanced propagation delays Inputs accepts voltages higher than VCC For AHC only: operates with CMOS input levels For AHCT only: operates with TTL input levels Output capability: standard ICC category: flip-flops Specified from −40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT74 dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. fma...