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74AHCT30 Datasheet

Part Number 74AHCT30
Manufacturers NXP
Logo NXP
Description 8-input NAND gate
Datasheet 74AHCT30 Datasheet74AHCT30 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET 74AHC30; 74AHCT30 8-input NAND gate Product specification File under Integrated Circuits, IC06 1999 Nov 30 Philips Semiconductors Product specification 8-input NAND gate FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input le.

  74AHCT30   74AHCT30






Part Number 74AHCT30
Manufacturers nexperia
Logo nexperia
Description 8-input NAND gate
Datasheet 74AHCT30 Datasheet74AHCT30 Datasheet (PDF)

74AHC30; 74AHCT30 8-input NAND gate Rev. 5 — 6 May 2020 Product data sheet 1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Lowpower Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30; 74AHCT30 provides an 8-input NAND function. 2. Features and benefits • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Input levels: • For 74AHC30.

  74AHCT30   74AHCT30







8-input NAND gate

INTEGRATED CIRCUITS DATA SHEET 74AHC30; 74AHCT30 8-input NAND gate Product specification File under Integrated Circuits, IC06 1999 Nov 30 Philips Semiconductors Product specification 8-input NAND gate FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Output capability: standard • ICC category: SSI • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. DESCRIPTION 74AHC30; 74AHCT30 The 74AHC/AHCT30 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT30 provide the 8-input NAND function. TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PARAMETER propagation delay A, B, C, D, E, F, G, H to Y input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 3.6 3.0 4.0 10.


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