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74AHC573 Datasheet

Part Number 74AHC573
Manufacturers NXP
Logo NXP
Description Octal D-type transparent latch
Datasheet 74AHC573 Datasheet74AHC573 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Product specification File under Integrated Circuits, IC06 1999 Sep 27 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Common 3-state output enable input • Funct.

  74AHC573   74AHC573






Part Number 74AHC573
Manufacturers nexperia
Logo nexperia
Description Octal D-type transparant latch
Datasheet 74AHC573 Datasheet74AHC573 Datasheet (PDF)

74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Rev. 8 — 13 July 2020 Product data sheet 1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the informatio.

  74AHC573   74AHC573







Octal D-type transparent latch

INTEGRATED CIRCUITS DATA SHEET 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Product specification File under Integrated Circuits, IC06 1999 Sep 27 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Common 3-state output enable input • Functionally identical to the ‘563’ and ‘373’ • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. DESCRIPTION 74AHC573; 74AHCT573 The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. The ‘573’ consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input change.


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