74ACT16833

54ACT16833, 74ACT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCAS166A – JUNE 1990 – REVISED APRIL 1996 D Members of the Texas Instruments Widebus ™ Family D Inputs Are TTL-Voltage Compatible D Parity Error Flag With Parity Generator/Checker D Register for Storage of the Parity Error Flag D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’ACT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY or 2PARITY is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected. 54ACT16833 . . . WD PACKAGE 74ACT16833 . . . DL PACKAGE (TOP VIEW) 1OEB 1 1CLK 2 1ERR 3 GND 4 1A1 5 1A2 6 VCC 7 1A3 8 1A4 9 1A5 10 GND 11 1A6 12 1A7 13 1A8 14 2A1 15 2A2 16 2A3 17 GND 18 2A4 19 2A5 20 2A6 21 VCC 22 2A7 23 2A8 24 GND 25 2ERR 26 2CLK 27...