74ACT11825

74ACT11825 8-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS154A – D3715, NOVEMBER 1990 – REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Multiple Output Enables Allow Multiuser Control of the Interface Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C description This device contains eight flip-flops that feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers. DW PACKAGE (TOP VIEW) OE1 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q CLR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 OE2 27 OE3 26 1D 25 2D 24 3D 23 4D 22 VCC 21 VCC 20 5D 19 6D 18 7D 17 8D 16 CLKEN 15 CLK With the clock-enable (CLKEN) input low, the eight edge-triggered D-type flip-flops enter data on the low-to-high transition of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. The 74ACT11825 has noninverting data (D) inputs. Taking the clear (CLR) input low causes the eight Q outputs to go low independently of the clock. Multiuser buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-imp...