74AC11643

Bidirectional Bus Transceivers in High-Density 24-Pin Packages Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description 74AC11643 OCTAL BUS TRANSCEIVER WITH 3–STATE OUTPUTS SCAS057A – JULY 1987 – REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 10 11 12 24 DIR 23 B1 22 B2 21 B3 20 B4 19 VCC 18 VCC 17 B5 16 B6 15 B7 14 B8 13 OE These octal bus transceivers are designed for asynchronous communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The 74AC11643 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus HX Isolation logic symbol† 13 OE 24 DIR 1 A1 2 A2 3 A3 4 A4 9 A5 10 A6 11 A7 12 A8 G3 3 EN1 [BA] 3 EN2 [AB] 11 12 23 B1 22 B2 21 B3 20 B4 17 B5 16 B6 15 B7 14 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA inform...