• Generates Either Odd or Even Parity for
Nine Data Lines
• Cascadable for n-Bits Parity • Direct Bus Connection for Par...
Generates Either Odd or Even Parity for
Nine Data Lines
Cascadable for n-Bits Parity Direct Bus Connection for Parity
Generation or for Checking by Using the
Parity I/O Port
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
t EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
74AC11286 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
D OR N PACKAGE (TOP VIEW)
B A PARITY I/O GND PARITY ERROR XMIT I
1 2 3 4 5 6 7
14 C 13 D 12 E 11 VCC 10 F 9G 8H
description
The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
The XMIT control input is implemented specifically to accommodate cascading. When the XMIT is low, the parity tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels. When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O cont...