74AC11191

74AC11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER Single Down/Up Count Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable with Load Control Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs SCAS105A – FEBRUARY 1990 – REVISED APRIL 1993 DW OR N PACKAGE (TOP VIEW) RCO QA QB GND GND GND GND QC QD MAX/MIN 1 2 3 4 5 6 7 8 9 10 20 D/U 19 CLK 18 A 17 B 16 VCC 15 VCC 14 C 13 D 12 CTEN 11 LOAD description The 74AC11191 is a synchronous, 4-bit binary reversible up/down counter. Synchronous counting operation is provided by clocking all flip-flops simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. These counters feature a fu...