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74ABT74 Datasheet

Part Number 74ABT74
Manufacturers nexperia
Logo nexperia
Description Dual D-type flip-flop
Datasheet 74ABT74 Datasheet74ABT74 Datasheet (PDF)

74ABT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 3 — 12 October 2020 Product data sheet 1. General description The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. This device is fully spe.

  74ABT74   74ABT74






Part Number 74ABT74
Manufacturers NXP
Logo NXP
Description Dual D-type flip-flop
Datasheet 74ABT74 Datasheet74ABT74 Datasheet (PDF)

Philips Semiconductors Dual D-type flip-flop Product specification 74ABT74 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V tPLH tPHL tOSLH tOSHL CIN Propagation delay CPn to Qn, Qn Output to Output skew Input capacitance CL = 50pF; VCC = 5V VI = 0V or VCC ICC Total supply current Outputs disabled; VCC = 5.5V TYPICAL UNIT 3.0 2.5 ns 0.5 ns 3 pF 50 µA PIN CONFIGURATION DESCRIPTION The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring indivi.

  74ABT74   74ABT74







Dual D-type flip-flop

74ABT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 3 — 12 October 2020 Product data sheet 1. General description The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Supply voltage range from 4.5 V to 5.5 V • BiCMOS high speed and output drive • Direct interface with TTL levels • Power-up 3-state • IOFF circuitry provides partial Power-down mode operation • Latch-up protection exceeds 500 mA per JESD78B class II level A • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74ABT74D -40 °C to +85 °C SO14 74ABT74PW -40 °C to +85 °C TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 Nexperia 4. Functional diagram 4 10 1SD 2SD SD 2 12 1D 2D .


2019-07-23 : BC817K    BAS21TH    MMZ0603AFY560VT000    BAS16TH    74AHC123A    74ABT74    74ALVT16823    74LV123    74LV4060    74HCT4538   


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