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74ABT646A Datasheet

Part Number 74ABT646A
Manufacturers NXP
Logo NXP
Description Octal bus transceiver/register
Datasheet 74ABT646A Datasheet74ABT646A Datasheet (PDF)

74ABT646A Octal bus transceiver/register; 3-state Rev. 03 — 15 March 2010 Product data sheet 1. General description The 74ABT646A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A .

  74ABT646A   74ABT646A






Part Number 74ABT646
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Octal Transceivers/Registers
Datasheet 74ABT646A Datasheet74ABT646 Datasheet (PDF)

74ABT646 Octal Transceivers and Registers with 3-STATE Outputs April 1992 Revised November 1999 74ABT646 Octal Transceivers and Registers with 3-STATE Outputs General Description The ABT646 consists of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic lev.

  74ABT646A   74ABT646A







Octal bus transceiver/register

74ABT646A Octal bus transceiver/register; 3-state Rev. 03 — 15 March 2010 Product data sheet 1. General description The 74ABT646A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A bus or B bus will be clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH. Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the A or B register or both. The Select (SAB, SBA) pins determine whether data is stored or transferred through the device in real-time. The DIR pin determines which bus receives data when OE is active (LOW)..


2005-04-03 : STK4110    STK4111    STK4112    4511    4511B    FQ08E    2SC4491    2SC4492    2SC4493    2SC4495   


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