7476

DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs September 1986 Revised July 2001 DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic state of J and K inputs must not be allowed to change while the clock is HIGH. The data is transferred to the outputs on the falling edge of the clock pulse. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Function Table Inputs Outputs PR CLR CLK J K Q Q LHXXX H L HLXXX L H L LXXX H H H H H H H H H H (Note 1) (Note 1) L L Q0 Q0 HL H L LH L H HH Toggle H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Positive pulse data. The J and K inputs m...