www.DataSheet4U.com
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor Logic level FET
FEAT...
www.DataSheet4U.com
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor Logic level FET
FEATURES
’Trench’ technology Very low on-state resistance Fast switching Low thermal resistance Logic level compatible
PHP55N03LT, PHB55N03LT PHD55N03LT
QUICK REFERENCE DATA
d
SYMBOL
VDSS = 25 V ID = 55 A RDS(ON) ≤ 14 mΩ (VGS = 10 V) RDS(ON) ≤ 18 mΩ (VGS = 5 V)
g
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. Applications: High frequency computer motherboard d.c. to d.c. converters High current switching The PHP55N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB55N03LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD55N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
PIN 1 2 3 tab DESCRIPTION gate drain 1 source
SOT78 (TO220AB)
tab
SOT404 (D2PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM Ptot Tj, Tstg Drain-source
voltage Drain-gate
voltage Gate-source
voltage (DC) Gate-source
voltage (pulse peak value) Drain current (DC) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tj ≤ 150˚C Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚...