54F825

54F 74F825 8-Bit D-Type Flip-Flop December 1994 54F 74F825 8-Bit D-Type Flip-Flop General Description The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface The ’F825 is functionally and pin compatible with AMD’s Am29825 Features Y TRI-STATE output Y Clock enable and clear Y Multiple output enables Y Direct replacement for AMD’s Am24825 Commercial Military Package Number Package Description 74F825SPC N24C 24-Lead (0 300 Wide) Molded Dual-In-Line 54F825SDM (Note 2) J24F 24-Lead (0 300 Wide) Ceramic Dual-In-Line 74F825SC (Note 1) M24B 24-Lead (0 300 Wide) Molded Small Outline JEDEC 54F825FM (Note 2) W24C 24-Lead Cerpack 54F825LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX Note 2 Military grade device with environmental and burn-in processing Use suffix e SDMQB FMQB and LMQB Logic Symbols IEEE IEC Obsolete TL F 9597 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9597 TL F 9597 – 4 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9597–2 Unit Loading Fan Out Pin Names D0 – D7 O0 – O7 OE1 OE2 OE3 EN CLR CP Description Data Inputs TR...