54F138

SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception D Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description The ′F138 is designed to be used in high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. SDFS051B – MARCH 1987 – REVISED JULY 1996 SN54F138 . . . J PACKAGE SN74F138 . . . D OR N PACKAGE (TOP VIEW) A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 SN54F138 . . . FK PACKAGE (TOP VIEW) Y0 VCC NC A B C G2A NC G2B G1 3 2 1 20 19 4 18 Y1 5 17 Y2 6 16 NC 7 15 Y3 8 14 Y4 9 10 11 12 13 Y5 Y6 NC GND Y7 The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or NC – No internal connection inverters...