54ACT11027

Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain three independent 3-input NOR gates. They perform the Boolean functions Y = A + B + C or Y = ASBSC in positive logic. The 54ACT11027 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11027 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each gate) INPUTS A B C OUTPUT Y H X X L X H X L X X H L L L L H logic symbol† 1A 1 ≥1 1B 16 2 1Y 1C 15 2A 14 2B 11 3 2Y 2C 10 3A 9 3B 8 6 3Y 3C 7 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 54ACT11027, 74ACT11027 TRIPLE 3-INPUT POSITIVE-NOR GATES SCAS020A – D2957, JULY 1987 – REVISED APRIL 1993 54ACT11027 . . . J PACKAGE 74ACT11027 . . . D OR N PACKAGE (TOP VIEW) 1A 1 1Y 2 2Y 3 GND 4 GND 5 3Y 6 3C 7 3B 8 16 1B 15 1C 14 2A 13 VCC 12 VCC 11 2B 10 2C 9 3A 54ACT11027 . . . FK PACKAGE (TOP VIEW) 2A VCC NC VCC 2B 3 2 1 20 19 1C 4 18 2C 1B 5 17 3A NC 6 16 NC 1A 7 15 3B 1Y 8 14 3C 9 10 11 12 13 2Y GND NC GND 3Y N...