32N50Q

www.DataSheet4U.com HiPerFETTM Power MOSFETs ISOPLUS247TM (Electrically Isolated Back Surface) N-Channel Enhancement Mode High dV/dt, Low trr, HDMOSTM Family Preliminary data Symbol VDSS VDGR VGS VGSM ID25 IDM IAR EAS EAR dv/dt PD TJ TJM Tstg TL VISOL Weight 1.6 mm (0.062 in.) from case for 10 s 50/60 Hz, RMS t = 1 minute leads-to-tab Test Conditions TJ = 25°C to 150°C TJ = 25°C to 150°C; RGS = 1 MW Continuous Transient TC = 25°C TC = 25°C, Pulse width limited by TJM TC = 25°C TC = 25°C TC = 25°C IS £ IDM, di/dt £ 100 A/ms, VDD £ VDSS TJ £ 150°C, RG = 2 W TC = 25°C VDSS IXFR 30N50Q IXFR 32N50Q ID25 RDS(on) 0.16 W 0.15 W 500 V 29 A 500 V 30 A trr £ 250 ns Maximum Ratings 500 500 ±20 ±30 30N50 32N50 30N50 32N50 30N50 32N50 30 120 30 1.5 45 5 310 -55 ... +150 150 -55 ... +150 300 2500 6 V V V V A A A J mJ V/ns W °C °C °C °C V~ g ISOPLUS 247TM E 153432 G D Isolated back surface* G = Gate S = Source * Patent pending D = Drain Features Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation Low drain to tab capacitance(<50pF) Low RDS (on) HDMOSTM process Rugged polysilicon gate cell structure Unclamped Inductive Switching (UIS) rated Fast intrinsic Rectifier Applications Symbol Test Conditions Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. 500 2 4 ±100 TJ = 25°C TJ = 125°C 30N50 32N50 100 1 0.16 0.15 V V nA mA mA W W Advantages Easy assembly Space savings...