MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer's
HDTMOS E-FET .™ High Density Power FET DPAK for Surface Mount N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor .
MTD20N03HL
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MTD20N03HDL/D
Designer's
HDTMOS E-FET .™ High Density Power FET DPAK for Surface Mount N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits www.DataSheet4U.com where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size Operating and .