TL16C550
TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
D Capable of Running With All...
Description
TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
D Capable of Running With All Existing
TL16C450 Software
D Fully Programmable Serial Interface
Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 256 Kbit/s)
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU
D False-Start Bit Detection D Complete Status Reporting Capabilities D 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D In the TL16C450 Mode, Holding and Shift
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Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data Division of Any Input Reference Clock by 1 to (216 – 1) and Generates an Internal 16 × Clock
D Programmable Baud Rate Generator Allows
D Line Break Generation and Detection D Internal Diagnostic Capabilities:
– Loopback Controls for Communications Link Fault Isolation – Break, Parity, Overrun, Framing Error Simulation
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
D Fully Prioritized Interrupt System Controls D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Independent Receiver Clock Input D Transmit, Receive, Line Status, and Data
Se...
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