N-Channel Power MOSFET - ON Semiconductor
Description
TMOS E−FET.
™ Power Field Effect Transistor
N−Channel Enhancement−Mode Silicon Gate
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time.
In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes.
This new energy efficient design also offers a drain−to−source
diode with a fast recovery time.
Designed for low voltage, high speed
switching applications in power supplies, converters, PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
• IDSS and VDS(on) Specified at Elevated Temperature
D S
MTP8N50E
TMOS POWER FET 8.
0 AMPERES 500 VOLTS
RDS(on) = 0.
8 OHM
CASE 221A−09, Style 5 TO-220AB
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.
0 MW)
Gate−to−Source Voltage − Continuous Gate−to−Source Voltage − Non−repetitive (tp ≤ 10 ms)
Drain Current — Continuous @ TC = 25°C Drain Current — Continuous @ TC = 100°C Drain Current — Single Pulse (tp ≤ 10 ms)
Total Power Dissipation @ TC = 25°C Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy − STARTING TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.
0 Apk, L = 16 mH, RG = 25 W)
Thermal Resistance − Junction−to−Case − Junction−to−Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 sec.
Symbol
VDSS VDGR VGS VGSM
ID ID IDM PD
TJ, Tstg EAS
Value
500
500
±20 ±40
8.
0 5.
0 32
125 1.
0
−55 to 150
510
Unit Vdc Vdc Vdc Vpk Adc
Apk Watts W/°C
°C mJ
RqJC RqJA
TL
...
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