32K / 64K x 16 Dual-Port Static RAM - Cypress Semiconductor
Description
CY7C02732 K / 64 K × 16 Dual-Port Static RAM
CY7C027 CY7C028
32 K / 64 K × 16 Dual-Port Static RAM
32 K / 64 K × 16 Dual-Port Static RAM
Features
True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32 K × 16 organization (CY7C027) ■ 64 K × 16 organization (CY7C028) ■ 0.
35 micron CMOS for optimum speed and power ■ High speed access: 15 and 20 ns ■ Low operating power ■ Active: ICC = 180 mA (typical) ■ Standby: ISB3 = 0.
05 mA (typical) ■ Fully asynchronous operation ■ Automatic power down
■
■ ■ ■ ■ ■ ■ ■ ■ ■ ■
Expandable data bus to 32 bits or more using Master/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flags for port-to-port communication Separate upper-byte and lower-byte control Dual chip enables Pin select for Master or Slave Commercial and industrial temperature ranges Available in 100-pin TQFP Pb-free packages available
R/WR UBR
Logic Block Diagram
R/WL UBL
CE0L CE1L LBL OEL
CEL
CER
CE0R CE1R LBR OER
I/O8L–I/O15L I/O0L–I/O7L
[2]
[1]
8 8
8
I/O Control
I/O Control
8
I/O8L–I/O15R I/O0L–I/O7R
[2]
[1]
A0L–A14/15L
[3]
15/16
Address Decode
15/16
True Dual-Ported RAM Array
Address Decode
15/16
15/16
A0R–A14/15R
[3]
A0L–A14/15L CEL OEL R/WL SEML BUSYL[4] INTL UBL LBL
Notes 1.
I/O8–I/O15 for × 16 devices 2.
I/O0–I/O7 for × 16 devices 3.
A0–A14 for 32K; A0–A15 for 64K devices.
4.
BUSY is an output in master mode and an input in slave mode.
[3]
Interrupt Semaphore Arbitration
A0R–A14/15R CER OER R/WR SEMR
[4]
[3]
M/S
BUSYR INTR UBR LBR
Cypress Semiconductor Corporation Document Number: 38-06042 Rev.
*J
•
198 Champion Court
•
San Jose, CA 95134-1709 • 408-943-2600 Revised August 28, 2013
CY7C027 CY7C028
Functional Description
The CY7C027 and CY7C028 are low power CMOS 32 K, 64 K × 16 dual-port static RAMs.
Various arbitration schemes are included on the devices to handle situations when multiple...
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