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HD74ALVCH162501

Hitachi Semiconductor
Part Number HD74ALVCH162501
Manufacturer Hitachi Semiconductor
Description 18-bit Universal Bus Transceivers with 3-state Outputs
Published Mar 23, 2005
Detailed Description HD74ALVCH162501 18-bit Universal Bus Transceivers with 3-state Outputs ADE-205-182 (Z) Preliminary 1st. Edition Decembe...
Datasheet PDF File HD74ALVCH162501 PDF File

HD74ALVCH162501
HD74ALVCH162501

Overview
HD74ALVCH162501 18-bit Universal Bus Transceivers with 3-state Outputs ADE-205-182 (Z) Preliminary 1st.
Edition December 1996 Description Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs.
For A to B data flow, the device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level.
If LEAB is low, the A bus data is stored in the latch flip flop on the low to high transition of CLKAB.
When OEAB is high, the outputs are active.
When OEAB is low, the outputs are in the high impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA , LEBA, and CLKBA.
The output enables are complementary (OEAB is active high, and OEBA is active low).
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot.
Features • VCC = 2.
3 V to 3.
6 V • Typical VOL ground bounce < 0.
8 V (@VCC = 3.
3 V, Ta = 25°C) • Typical VOH undershoot > 2.
0 V (@VCC = 3.
3 V, Ta = 25°C) • High output current ±12 mA (@VCC = 3.
0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors • All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162501 Function Table *3 Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X ↑ ↑ H L A X L H L H X X Z L H L H B0 B0 *1 *2 Output B H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1.
Output level before the indicated steady state input conditions were established, provided that CLKAB was high before LEAB went low.
2.
Output level before the indicated steady state input conditions were established.
3.
A to B data flow is show; B to A flow is similar but uses OEBA, LEBA, and CLKBA.
HD74ALVCH162501 Pin Arrangem...


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