Clock Generator - Cypress Semiconductor
Description
PRELIMINARY
CY28RS480-1
Clock Generator for ATI RS480 Chipset
Features
• Supports AMD CPU • Selectable CPU frequencies • 200-MHz differential CPU clock pairs • 100-MHz differential SRC clocks • 48-MHz USB clock • 33-MHz PCI clock • 66-MHz HyperTransport clock • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.
3V power supply • 56-pin SSOP and TSSOP packages CPU x2 SRC x8 HTT66 x1 PCI x1 REF x3 USB_48 x1
Block Diagram
XIN XOUT CPU_STP# CLKREQ[0:1]#
Pin Configuration
VDD_REF REF[0:2] VDD_CPU CPUT[0:2], CPUC[0:2], VDD_SRC SRCT[0:6],SRCC[0:6] VDD_SRCS SRCST[0:1],SRCSC[0:1] VDD_PCI PCI VDD_HTT HTT66
www.
DataSheet.
co.
kr
XTAL OSC PLL1
PLL Ref Freq
Divider Network
IREF
PD
VDD_48 MHz
PLL2
USB_48
SDATA SCLK
I2C Logic
XIN XOUT VDD_48 USB_48 VSS_48 CLK_STOP SCLK SDATA NC CLKREQ#0 CLKREQ#1 SRCT5 SRCC5 VDD_SRC VSS_SRC SRCT4 SRCC4 SRCT3 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDD_REF VSS_REF REF0 REF1 REF2 VDD_PCI PCI0 VSS_PCI VDD_HTT HTT66 VSS_HTT CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 VDDA VSSA IREF VSS_SRC VDD_SRC SRCT0 SRCC0 VDD_SRC1 VSS_SRC1 SRCST0 SRCSC0
56 SSOP/TSSOP
Cypress Semiconductor Corporation Document #: 38-07714 Rev.
*C
•
3901 North First Street
•
San Jose, CA 95134 • 408-943-2600 Revised August 4, 2005
Datasheet pdf - http://www.
DataSheet4U.
net/
CY28RS480-1
PRELIMINARY
Pin Description
Pin No.
41,40,45,44 50 37 52, 53, 54 7 8 27, 28, 30, 29 12, 13, 16, 17, 18, 19, 22, 23, 24, 25, 34, 33 10,11 Name CPUT/C PCI0 IREF REF[2:0] SCLK SDATA SRCST/C[1:0] SRCT/C[5:0] Type O I 33-MHz clock output.
Description
CY28RS480-1
O, DIF Differential CPU clock outputs.
AMD K8 buffer (200 MHz).
A precision resistor attached to this pin is connected to the internal current reference...
Similar Datasheet
