DatasheetsPDF.com

TSI350

Tundra Semiconductor
Part Number TSI350
Manufacturer Tundra Semiconductor
Description PCI-to-PCI Bridge
Published Jan 27, 2011
Detailed Description Tsi350™ PCI-to-PCI Bridge Features PCI Interfaces • Industry-standard 32-bit, 66-MHz PCI bridge • Fully PCI Local Bus ...
Datasheet PDF File TSI350 PDF File

TSI350
TSI350


Overview
Tsi350™ PCI-to-PCI Bridge Features PCI Interfaces • Industry-standard 32-bit, 66-MHz PCI bridge • Fully PCI Local Bus Specification, Revision 2.
3 compliant • Supports up to nine PCI bus masters on the secondary interface • Ten independent secondary clock outputs to the secondary slots • Primary and secondary interfaces can be operated using asynchronous clocks • Secondary clock can either be derived from the input primary clock or supplied by an external clock source • Secondary clocks can be masked through the GPIO interface during power up The Tsi350 makes it possible to extend a system’s load capability limit beyond that of a single PCI bus by allowing motherboard designers to add more PCI devices or more PCI option card slots than a single PCI bus can support.
The Tundra Semiconductor Tsi350 is a PCI-to-PCI bridge that is fully compliant with PCI Local Bus Specification, Revision 2.
3.
The Tsi350 has sufficient clock and arbitration pins to support nine PCI bus master devices directly on its secondary interface.
The Tsi350 allows the two PCI buses to operate concurrently.
This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy.
This traffic isolation may increase system performance in applications such as multimedia.
The Tsi350 makes it possible to extend a system’s load capability limit beyond that of a single PCI bus by allowing motherboard designers to add more PCI devices or more PCI option card slots than a single PCI bus can support.
The Tsi350 has two identical PCI Interfaces that each handle PCI transactions for its respective bus, and, depending on the type of transaction, can act as either a bus master or a bus slave.
These interfaces transfer data and control information flowing to and from the blocks shown below.
Block Diagram IEEE1149.
1 Boundary Scan JTAG Clocking/ Reset Hot Swap Posted Write Buffer Primary PCI Bus Interface NonPosted Buffer Secondary PCI Bus Interface Mux Logic • Supports fo...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)