DatasheetsPDF.com

HY5DU12822DLTP

Part Number	HY5DU12822DLTP
Manufacturer	Hynix Semiconductor
Published	Dec 21, 2010
Description	512Mb DDR SDRAM
Detailed Description	512Mb DDR SDRAM HY5DU12822D(L)TP HY5DU121622D(L)TP This document is a general product description and is subject to cha...
Datasheet	HY5DU12822DLTP PDF File

Overview

512Mb DDR SDRAM HY5DU12822D(L)TP HY5DU121622D(L)TP This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
1 / Jan 2007 1 www.
DataSheet.
in 1Preliminary HY5DU12822DTP HY5DU121622DTP Revision History Revision No.
0.
1 History First version for internal review Draft Date Jan.
2007 Remark Rev.
0.
1 / Jan 2007 2 www.
DataSheet.
in 1Preliminary HY5DU12822DTP HY5DU121622DTP DESCRIPTION The HY5DU12822DT(P) and HY5DU121622DT(P) are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.
FEATURES • • VDD, VDDQ = 2.
3V min ~ 2.
7V max (Typical 2.
5V Operation +/- 0.
2V for DDR266, 333) VDD, VDDQ = 2.
4V min ~ 2.
7V max (Typical 2.
6V Operation +0.
1/- 0.
2V for DDR400 product ) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe • • • • • • All addresses and control inputs ex...

Similar Datasheet

HY5DU12822DLTP 512Mb DDR SDRAM - Hynix Semiconductor

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)