256M bits SDRAM WTR - Elpida Memory
Description
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DATA SHEET
256M bits SDRAM WTR (Wide Temperature Range)
EDS2532EEBH-75TT (8M words × 32 bits)
Specifications
• Density: 256M bits • Organization 2M words × 32 bits × 4 banks • Package: 90-ball FBGA Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.
8V ± 0.
1V • Clock frequency: 133MHz (max.
) • 2KB page size Row address: A0 to A11 Column address: A0 to A8 • Four internal banks for concurrent operation • Interface: LVCMOS • Burst lengths (BL): 1, 2, 4, 8, full page • Burst type (BT): Sequential (1, 2, 4, 8, full page) Interleave (1, 2, 4, 8) • /CAS Latency (CL): 2, 3 • Precharge: auto precharge operation for each burst access • Driver strength: half/quarter • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/64ms Average refresh period: 15.
6µs • Operating ambient temperature range TA = –20°C to +85°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
1 2 3 4 5 6 7 8 9
EO
Features
A
DQ26 DQ24 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0
/CAS
VDD
DQ6
DQ1
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC A3 A6 NC A9
NC
VSS
DQ16 VSSQ DQM2 VDD A0 BA1 /CS A1 A11 /RAS
F
VSS DQM3
• ×32 organization • Single pulsed /RAS • Burst read/write operation and burst read/single write operation capability • Byte control by DQM • Wide temperature range TA = –20°C to +85°C
Document No.
E0910E10 (Ver.
1.
0) Date Published May 2006 (K) Japan Printed in Japan URL: http://www.
elpida.
com
L
G
A4 A5 A8 CKE
NC
H
A7
J
CLK
This product became EOL in September, 2007.
Elpida Memory, Inc.
2006
Pr
K L M N P R
DQM1
/WE DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VDDQ DQ8
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
od
DQ13 DQ15 VSS
(Top view)
Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power for internal circuit Ground for inte...
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