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QL3025

Part Number	QL3025
Manufacturer	QuickLogic Corporation
Description	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Published	May 22, 2010
Detailed Description	QL3025 pASIC 3 FPGA Data Sheet •••••• 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density D...
Datasheet	QL3025 PDF File

Overview

QL3025 pASIC 3 FPGA Data Sheet •••••• 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 25,000 Usable PLD Gates with 204 I/Os • 300 MHz 16-bit www.
DataSheet4U.
com Four Low-Skew Distributed Networks • Two array clock/control networks available Counters, 400 MHz Datapaths • 0.
35 µm four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast Development Cycles • 100% routable with 100% utilization and to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin • Two global clock/control networks available to the logic cell; F1, clock set, reset inputs an...

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