1 PLL In-System Programmable Clock Generator - Cypress Semiconductor
Description
PRELIMINARY
CY22701
1 PLL In-System Programmable Clock Generator
Features
• In-system programmable through I2C Serial Programming Interface (SPI) • Programmable SRAM and non-volatile EEPROM memory bits with 3.
3V supply • Integrated, phase-locked loop with programmable P and Q counters, output dividers • Low-jitter, high-accuracy outputs • 3.
3V Operation www.
DataSheet4U.
com • 8-lead SOIC
Benefits
• Custom timing solutions for designs not suitable for factory custom silicon, Xtals, or ASICs for production • Program and optimize designs while chip is on system board • Programming voltages contained in chip • High-performance PLL enables control of output frequencies that are customizable to support a wide range of applications • Meets critical timing requirements in complex system designs • Meets industry-standard voltage platforms • Industry standard packaging saves on board space
Part Number CY22701
No.
of Outputs 2
Input Frequency Range
Output Frequency Range
1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.
3V) {Commercial} 1 –150 MHz (Driven Clock Input) {Industrial} 80 kHz –167 MHz (3.
3V) {Industrial} 8 – 30 MHz (Crystal Reference) {Comm.
or Ind.
}
Logic Block Diagram
XIN XOUT OUTPUT DIVIDERS Output Crosspoint Switch Array
OSC
Q
Φ VCO P PLL
CLK1 CLK2
Clock Configuration
EEPROM Memory Array
Pin Configuration
WP [I2C- SPI:] SCL SDAT
XIN VDD
VDD VSS
1 2 3 4
8 XOUT CY22701 7 CLK2/WP 6 CLK1 5 SCL 8 PIN SOIC
SDA VSS
Cypress Semiconductor Corporation Document #: 38-07698 Rev.
*B
•
3901 North First Street
•
San Jose, CA 95134 • 408-943-2600 Revised February 8, 2005
PRELIMINARY
Pin Description
Name XIN VDD SDAT VSS SCL CLK1 CLK2/WP XOUT[1] Pin Number 1 2 3 4 5 6 7 8 Description Reference crystal input 3.
3V voltage supply Data input for serial programming Ground Clock signal input for serial programming Clock output 1 (Default to reference frequency) Clock output 2/Write Protect (Default Write Protect) Reference crystal output
CY2...
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