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HYB18T512800BC

Qimonda
Part Number HYB18T512800BC
Manufacturer Qimonda
Description 512-Mbit Double-Data-Rate-Two SDRAM
Published Dec 17, 2009
Detailed Description May 2007 HYB18T512400B[C/F] HYB18T512800B[C/F] HYB18T512160B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS C...
Datasheet PDF File HYB18T512800BC PDF File

HYB18T512800BC
HYB18T512800BC

Overview
May 2007 HYB18T512400B[C/F] HYB18T512800B[C/F] HYB18T512160B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products www.
DataSheet4U.
com Internet Data Sheet Rev.
1.
1 Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512400B[C/F], HYB18T512160B[C/F], HYB18T512800B[C/F] Revision History: 2007-05, Rev.
1.
1 Page All All All Subjects (major changes since last revision) Adapted internet edition Added more product types Qimonda template update Previous Revision: 2007-01, Rev.
1.
05 Previous Revision: 2006-02, Rev.
1.
04 www.
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com We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev400 / 3.
2 QAG / 2006-07-21 03292006-YBYM-WG0Z 2 Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.
1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On• 1.
8 V ± 0.
1 V Power Supply 1.
8 V ± 0.
1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organizations with 4 and 8 data in/outputs • Auto-Precharge operation for read and write bursts • Double-Data-Rate-Two architecture: two data transfers • Auto-Refresh, Self-Refresh and power saving Powerper clock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.
8 µs at a TCASE lower than • Programmable Burst Length: 4 and 8 85 °C, 3.
9 µs between 85 °C and 95 °C • Differential clock inputs (CK and CK) • Programmable self refresh rate via EMRS2 setting • Programmabl...


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