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HYB18T1G800BC

Qimonda
Part Number HYB18T1G800BC
Manufacturer Qimonda
Published Apr 2, 2009
Description 1-Gbit Double-Data-Rate-Two SDRAM
Detailed Description May 2007 www.DataSheet4U.com HY[B/I]18T1G400B[F/C](L) HY[B/I]18T1G800B[F/C](L) HY[B/I]18T1G160B[F/C](L) 1-Gbit Double-...
Datasheet PDF File HYB18T1G800BC PDF File

HYB18T1G800BC
HYB18T1G800BC


Overview
May 2007 www.
DataSheet4U.
com HY[B/I]18T1G400B[F/C](L) HY[B/I]18T1G800B[F/C](L) HY[B/I]18T1G160B[F/C](L) 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.
1.
2 Internet Data Sheet www.
DataSheet4U.
com HY[B/I]18T1G[40/80/16]0B[C/F](L) 1-Gbit Double-Data-Rate-Two SDRAM HY[B/I]18T1G400B[F/C](L), HY[B/I]18T1G160B[F/C](L), HY[B/I]18T1G800B[F/C](L) Revision History: 2007-05, Rev.
1.
2 Page All Subjects (major changes since last revision) Adapted internet edition Added products with industrial temperature range Added HYB18T1G400BFL-3S, HYB18T1G800BFL-3S, HYB18T1G160BFL-3S, HYB18T1G400BFL-25F, HYB18T1G800BFL-25F, HYB18T1G160BFL-25F Previous Revision: 2007-03, Rev.
1.
1 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev400 / 3.
2 QAG / 2006-07-21 03062006-ZNH8-HURV 2 Internet Data Sheet www.
DataSheet4U.
com HY[B/I]18T1G[40/80/16]0B[C/F](L) 1-Gbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.
1 Features The 1-Gbit Double-data-Rate SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On• 1.
8 V ± 0.
1 V Power Supply 1.
8 V ± 0.
1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organizations with 4, 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.
8 µs at a TCASE lower than • Programmable Burst Length: 4 and 8 85 °C, 3.
9 µs...


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