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ICS83947I-147

Integrated Circuit Systems

1-TO-9 LVCMOS FANOUT BUFFER - Integrated Circuit Systems


ICS83947I-147
ICS83947I-147

PDF File ICS83947I-147 PDF File



Description
Integrated Circuit Systems, Inc.
ICS83947I-147 LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER FEATURES • 9 LVCMOS/LVTTL outputs • Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum output frequency: 250MHz • Output skew: 115ps (maximum) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.
02ps (typical) @ 3.
3V • Full 3.
3V or 2.
5V operating supply • -40°C to 85°C ambient operating temperature • Pin compatible with the MPC947 GENERAL DESCRIPTION The ICS83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS.
The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased from 9 to 18 by utilizing the ability of the outputs to drive two series terminated lines.
ICS www.
DataSheet4U.
com Guaranteed output and part-to-part skew characteristics make the ICS83947I-147 ideal for high performance, 3.
3V or 2.
5V single ended applications.
BLOCK DIAGRAM CLK_EN D Q LE CLK0 CLK1 0 PIN ASSIGNMENT GND GND GND VDDO VDDO Q0 Q1 Q2 32 31 30 29 28 27 26 25 Q0 GND CLK_SEL Q1 CLK0 CLK1 CLK_EN Q3 Q4 Q5 Q6 Q7 Q8 OE VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND VDDO Q8 GND Q7 VDDO Q6 GND 24 23 22 GND Q3 VDDO Q4 GND Q5 VDDO GND 1 CLK_SEL Q2 ICS83947I-147 21 20 19 18 17 32-Lead LQFP 7mm x 7mm x 1.
4mm package body Y Package Top View OE 83947AYI-147 http://www.
icst.
com/products/hiperclocks.
html 1 REV.
A SEPTEMBER 24, 2004 Integrated Circuit Systems, Inc.
ICS83947I-147 LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER Name GND Type Power Input Input Input Input Power Pullup Description Power supply ground.
Clock select input.
When HIGH, selects CLK1.
When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
Pullup Reference clock inputs.
LVCMOS / LVTTL interface levels.
TABLE 1.
PIN DESCRIPTIONS Number 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, ...



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