(MT47HxxxMxx) DDR2 SDRAM - Micron
Description
2Gb: x4, x8, x16 DDR2 SDRAM Features
DDR2 SDRAM
MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks Features
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• • • • • • • • • • • • • • • • •
Vdd = +1.
8V ±0.
1V, VddQ = +1.
8V ±0.
1V JEDEC-standard 1.
8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option 4n-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 DLL to align DQ and DQS transitions with CK 8 internal banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 tCK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,192-cycle refresh On-die termination (ODT) Industrial temperature (IT) option RoHS compliant Supports JEDEC clock jitter specification
• Configuration – 512 Meg x 4 (64 Meg x 4 x 8 banks) – 256 Meg x 8 (32 Meg x 8 x 8 banks) – 128 Meg x 16 (16 Meg x 16 x 8 banks) • FBGA package (Pb-free) – x16 – 84-ball FBGA (11.
5mm x 14mm) Rev.
A • FBGA package (Pb-free) – x4, x8 – 60-ball FBGA (11.
5mm x 14mm) Rev.
A • Timing – cycle time – 3.
0ns @ CL = 4 (DDR2-667) – 3.
0ns @ CL = 5 (DDR2-667) – 3.
75ns @ CL = 4 (DDR2-533) – 5.
0ns @ CL = 3 (DDR2-400) • Self refresh – Standard – Low-power • Operating temperature – Commercial (0°C ≤ TC ≤ 85°C) – Industrial (–40°C ≤ TC ≤ 95°C; –40°C ≤ TA ≤ 85°C) Revision •
Note:
Options1
Marking
512M4 256M8 128M16 HG HG -3E -3 -37E -5E None L None IT :A
1.
Not all options listed can be combined to define an offered product.
Use the Part Catalog Search on www.
micron.
com for product offerings and availability.
Table 1: Key Timing Parameters
Data Rate (MHz) Speed Grade -3E -3 -37E -5E CL = 3 400 400 400 400 CL = 4 667 533 533 400 CL = 5 667 667 n/a n/a
tRCD
(ns)
tRP
(ns)
tRC
(ns)
12 15 15 15
12 15 15 15
54 55 55 55
PDF: 09005aef824f87b6 Rev.
B 9/08 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
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