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PLL102-108

Part Number	PLL102-108
Manufacturer	PhaseLink Corporation
Description	Programmable DDR Zero Delay Clock Driver
Published	Oct 28, 2008
Detailed Description	PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM...
Datasheet	PLL102-108 PDF File

Overview

PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
• Distributes one clock Input to one bank of ten differential outputs.
• Track spread spectrum clocking for EMI reduction.
• Programmable delay between CLK_INT and CLK[T/C] from –0.
8ns to +3.
1ns by programming www.
DataSheet4U.
com CLKINT and FBOUT skew channel, or from –1.
1ns to +3.
5ns if additional DDR skew channels are enabled.
• Four independent programmable DDR skew channels from –0.
3ns to +0.
4ns with step size ± 100ps.
• Support 2-wire I2C serial bus interface.
• 2.
5V Operating Voltage.
• Available in 48-Pin 300mil SSOP.
• PIN CONFIGURATION GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD SDATA N/C FB_INT VDD FB_OUTT N/C GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND PLL102-108 DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output.
Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT.
The PLL can be bypassed for test purposes by strapping AV dd to ground.
BLOCK DIAGRAM Programmable Skew Channel -600~+800ps ±200ps step -300~+400ps ±100ps step AV DD Programmable Delay Channel CLK_INT (0~2.
5ns) +170ps step Control Logic FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT5 CLKC5 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT6 CLKC6 PLL FB_INT AV DD -300~+400ps ±100ps step -300~+400ps ±100ps step -300~+400ps ±100ps step 47745 Fremont Blvd.
, Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 1 PLL102-108 Programmable DDR Zero Delay Clock Driver PIN DESCRIPTIONS Name VDD ...

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