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PLL102-10

Part Number	PLL102-10
Manufacturer	PhaseLink Corporation
Description	Low Skew Output Buffer
Published	Oct 28, 2008
Detailed Description	PLL102-10 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spec...
Datasheet	PLL102-10 PDF File

Overview

PLL102-10 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz.
Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
www.
DataSheet4U.
com • Less than 100 ps cycle - cycle jitter.
• 2.
5V or 3.
3V power supply operation.
• Available in 8-Pin SOIC or MSOP package.
• • PIN CONFIGURATION REFIN GND CLK1 CLK2 1 8 CLKOUT DNC DNC VDD PLL102-10 2 3 4 7 6 5 DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package...

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