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MC74VHC157

Motorola
Part Number MC74VHC157
Manufacturer Motorola
Description Quad 2-Channel Multiplexer
Published Apr 14, 2007
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Channel Multiplexer The MC74VHC157 is an advanced high speed CMOS quad 2–...
Datasheet PDF File MC74VHC157 PDF File

MC74VHC157
MC74VHC157

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Channel Multiplexer The MC74VHC157 is an advanced high speed CMOS quad 2–channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2–input digital multiplexers with common select (S) and enable (E) inputs.
When E is held High, selection of data is inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• • • • • • • • • • • High Speed: tPD = 4.
1ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.
5V Operating Range Low Noise: VOLP = 0.
8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 82 FETs or 20 Equivalent Gates EXPANDED LOGIC DIAGRAM 2 A0 B0 A1 B1 NIBBLE INPUTS A2 B2 A3 B3 E S 10 14 13 15 1 12 Y3 9 Y2 3 5 6 11 7 Y1 DATA OUTPUTS 4 Y0 www.
DataSheet4U.
com MC74VHC157 D SUFFIX 16–LEAD SOIC PACKAGE CASE 751B–05 DT SUFFIX 16–LEAD TSSOP PACKAGE CASE 948F–01 M SUFFIX 16–LEAD SOIC EIAJ PACKAGE CASE 966–01 ORDERING INFORMATION MC74VHCXXXD MC74VHCXXXDT MC74VHCXXXM SOIC TSSOP SOIC EIAJ PIN ASSIGNMENT S A0 B0 Y0 A1 B1 Y1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC E A3 B3 Y3 A2 B2 Y2 FUNCTION TABLE Inputs E S Outputs Y0 – Y3 H X L L L A0 – A3 L H B0 – B3 A0 – A3, B0 – B3 = the levels of the respective Data–Word Inputs.
6/97 © Motorola, Inc.
1997 1 REV 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ...


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