DatasheetsPDF.com

HY5V52FP

Hynix Semiconductor
Part Number HY5V52FP
Manufacturer Hynix Semiconductor
Description 4Banks x 2M x 32bits Synchronous DRAM
Published Jan 21, 2007
Detailed Description www.DataSheet4U.com Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Document Title 4Bank x 2M x ...
Datasheet PDF File HY5V52FP PDF File

HY5V52FP
HY5V52FP


Overview
www.
DataSheet4U.
com Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No.
0.
1 History Initial Draft Draft Date Jun.
2004 Remark Preliminary This document is a general product description and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
1 / June.
2004 1 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM DESCRIPTION The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.
HY5V52(L)F(P) is organized as 4banks of 2,097,152x32.
HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs and outputs are synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth.
All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).
A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle.
(This pipelined design is not restricted by a '2N' rule) FEATURES • • • • • • Voltage : VDD, VDDQ 3.
3V All device pins are compatible with LVTTL interface 90Ball FBGA with 0.
8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 • Internal four banks operation • Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks • • • Auto refresh and self refresh 4096 Refresh cycles / 64ms Programmable Burst Leng...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)