Single-Supply TTL/CMOS Comparator - Analog Devices
Description
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Rail-to-Rail, Fast, Low Power, 2.
5 V to 5.
5 V, Single-Supply TTL/CMOS Comparators Preliminary Technical Data ADCMP608/ACMP609
FEATURES
10 mV sensitivity rail to rail at VCC = 2.
5 V Input common-mode voltage from −0.
2 V to VCC + 0.
2 V Low glitch CMOS-/TTL-compatible output stage 30 ns propagation delay 1 mW at 2.
5 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection >60 dB −40C° to +125C° operation
FUNCTIONAL BLOCK DIAGRAMS
NONINVERTING INPUT +
ADCMP608
INVERTING INPUT –
Q OUTPUT
SDN
APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators
NONINVERTING INPUT
+
Q OUTPUT Q OUTPUT
ADCMP609
INVERTING INPUT –
LE/HYS
SDN
Figure 1.
GENERAL DESCRIPTION
The ADCMP608 and ADCMP609 are fast comparators fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from VEE − 0.
5 V to VCC + 0.
5 V, low noise, TTL-/CMOS-compatible output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs.
The devices offer 30 ns propagation delays driving a 15 pF load with 5 mV overdrive on 350/400 μA typical supply current.
A flexible power supply scheme allows the devices to operate with a single +2.
5 V positive supply and a −0.
5 V to +3.
0 V input signal range up to a +5.
5 V positive supply with a −0.
5 V to +6V input signal range.
Split input/output supplies, with no sequencing restrictions on the ADCMP609, support a wide input signal range while allowing independent output swing control.
+
The TTL-/CMOS-compatible output stage is designed to drive up to 15 pF with full rated timing specs and to degrade in a graceful and linear fashion as additional capacitance is added.
The comparator inp...
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