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32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC
Preliminary Technical Data
FEATURES
32-channel DAC in 13 mm × 13 mm 108-lead CSPBGA Guaranteed monotonic to 14 bits Buffered voltage outputs Output voltage span of 3. 5 V × VREF(+) Maximum output voltage span of 17. 5 V System calibration function allowing user-programmable offset and gain Pseudo differential outputs relative to REFGND Clear function to user-defined REFGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) DAC increment/decrement mode Channel grouping and addressing features
AD5378
Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2. 5 V to 5. 5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset Digital reset (RESET pin and soft reset function)
APPLICATIONS
Level setting in automatic test equipment (ATE) Variable optical attenuators (VOAs) Optical switches Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
VCC POWER-ON RESET RESET DCEN/WR SYNC/CS REG0 REG1 DB13 SCLK/DB12 DIN/DB11 14 VDD VSS AGND DGND LDAC VBIAS VREF1(+) VREF1(–) REFGND A1 VBIAS CLR
AD5378
/
INPUT 14 REG 0–1 14
/
m REG0–1 c REG0–1
14
/
DAC 14 REG 0–1
/
DAC 0–1
VOUT 0 VOUT 1
/
STATE MACHINE
14
INTERFACE
DB0 A7
/
INPUT 14 REG 2 14
/
m REG2 c REG2
14
/
DAC 14 REG 2
/
DAC 2
VOUT 2
14
/
14
/
VOUT 3
A0 SER/PAR DIN SCLK SDO FIFOEN REFGND B1 REFGND B2 REFGND C1 REFGND C2 REFGND D1 REFGND D2 BUSY 14 14
/
INPUT 14 REG 5 14
/
m REG7 c REG7
14
/
DAC 14 REG 5
VOUT 4
/
DAC 5
VOUT 5
/ /
/
INPUT 14 REG 6–7
14
/
DAC 14 REG 6–7
/
DAC 6–7
VOUT 6 VOUT 7 VOUT 8 VOUT 31
05292-001
/
m REG8–9 c REG8–9
×4
VREF2(+) VREF2(–) REFGND A2
Figure 1.
Protected by U. S. Patent No. 5,969,657 and 6,823,416; other patents pending.
Rev. PrA
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AD5378 PDF File
