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NT5DS16M16CG

Part Number	NT5DS16M16CG
Manufacturer	Nanya Techology
Description	256Mb SDRAM
Published	Sep 24, 2006
Detailed Description	www.DataSheet4U.com NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NT5DS16M16CG Feature...
Datasheet	NT5DS16M16CG PDF File

Overview

www.
DataSheet4U.
com NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NT5DS16M16CG Features CAS Latency and Frequency CAS Latency 2 2.
5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2/2.
5(DDR333) , 2.
5/3(DDR400) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.
8ms Maximum Average Periodic Refresh Interval 2.
5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.
5V ± 0.
2V (DDR333) VDD = VDDQ = 2.
6V ± 0.
1V (DDR400) Available in Halogen and Lead Free packaging Description NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT, NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS, and NT5DS16M16CG are die C of 256Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 110 nm design process.
Read or Write command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations.
An Auto Precharge function may be enabled to provide a self-timed row precharge DataSheet4U.
com DataShee The 256Mb DDR SDRAM uses a double-data-rate architecthat is initiated at the end of the burst access.
ture to achieve high-speed operation.
The double data rate As with standard SDRAMs, the pipelined, multibank architecarchitecture is essentially a 2n prefetch architecture...

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