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EDD2516AKTA-5-E

Part Number	EDD2516AKTA-5-E
Manufacturer	Elpida Memory
Published	May 7, 2006
Description	256M bits DDR SDRAM (16M words x16 bits DDR400)
Detailed Description	( DataSheet : www.DataSheet4U.com ) DATA SHEET 256M bits DDR SD
Datasheet	EDD2516AKTA-5-E PDF File

Overview

( DataSheet : www.
DataSheet4U.
com ) DATA SHEET 256M bits DDR SDRAM EDD2516AKTA-5-E (16M words × 16 bits, DDR400) Description The EDD2516AKTA-5 is a 256M bits DDR SDRAM organized as 4,194,304 words × 16 bits × 4 banks.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Pin Configurations /xxx indicates active low signal.
66-pin Plastic TSOP(II) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS Features • Power supply: VDD, VDDQ = 2.
6V ± 0.
1V • Data rate: 400Mbps (max.
) • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver • Data inputs, outputs, and DM are synchronized with DQS • 4 internal banks for concurrent operation • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • SSTL_2 compatible I/O • Programmable burst length (BL): 2, 4, 8 • Programmable /CAS latency (CL): 3 • Programmable output driver strength: normal/weak • Refresh cycles: 8192 refresh cycles/64ms  7.
8µs maximum average periodic refresh interval • 2 variations of refresh  Auto refresh  Self refresh • TSOP (I...

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EDD2516AKTA-5-E 256M bits DDR SDRAM (16M words x16 bits DDR400) - Elpida Memory

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