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MIPS324KEP

MIPS Technologies
Part Number MIPS324KEP
Manufacturer MIPS Technologies
Description Processor Core
Published May 4, 2006
Detailed Description ( DataSheet : www.DataSheet4U.com ) MIPS32™ 4KEp™ Processor Core Datasheet November 8, 2002 The MIPS32™ 4KEp™ core fr...
Datasheet PDF File MIPS324KEP PDF File

MIPS324KEP
MIPS324KEP

Overview
( DataSheet : www.
DataSheet4U.
com ) MIPS32™ 4KEp™ Processor Core Datasheet November 8, 2002 The MIPS32™ 4KEp™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family.
It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications.
The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.
It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products.
The 4KEp core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
The 4KEp core implements the MIPS32 Release 2 Architecture with the MIPS16e™ ASE, and the 32-bit privileged resource architecture.
The Memory Management Unit (MMU) consists of a simple, Fixed Mapping Translation (FMT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer- (TLB-) based MMU.
Instruction and data caches are fully configurable from 0 - 64 Kbytes in size.
In addition, each cache can be organized as direct-mapped or 2-way, 3-way, or 4-way set associative.
Load and fetch cache misses only block until the critical word becomes available.
The pipeline resumes execution while the remaining words are being written to the cache.
Both caches are virtually indexed and physically tagged to allow them to be accessed in the same clock that the address is translated.
An optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data virtual address/value breakpoints.
Additionally, real-time tracing of instruction program counter, data address, and data values can be supported.
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