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MIPS324KM

MIPS Technologies
Part Number MIPS324KM
Manufacturer MIPS Technologies
Description Processor Core
Published May 4, 2006
Detailed Description ( DataSheet : www.DataSheet4U.com ) MIPS32 4Km™ Processor Core Datasheet March 6, 2002 The MIPS32™ 4Km™ core from MIP...
Datasheet PDF File MIPS324KM PDF File

MIPS324KM
MIPS324KM

Overview
( DataSheet : www.
DataSheet4U.
com ) MIPS32 4Km™ Processor Core Datasheet March 6, 2002 The MIPS32™ 4Km™ core from MIPS® Technologies is a member of the MIPS32 4K™ processor core family.
It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications.
The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.
It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products.
The 4Km core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
The 4Km core implements the MIPS32 Architecture and contains all MIPS II™ instructions; special multiply-accumulate (MAC), conditional move, prefetch, wait, and leading zero/one detect instructions; and the 32-bit privileged resource architecture.
The Memory Management Unit consists of a simple, fixed Block Address Translation (BAT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer based MMU.
The synthesizable 4Km core implements single cycle MAC instructions, which enable DSP algorithms to be performed efficiently.
The Multiply/Divide Unit (MDU) allows 32-bit x 16-bit MAC instructions to be issued every cycle.
A 32-bit x 32-bit MAC instruction can be issued every 2 cycles.
Instruction and data caches are fully configurable from 0 - 16 Kbytes in size.
In addition, each cache can be organized as direct-mapped or 2-way, 3-way, or 4-way set associative.
Load and fetch cache misses only block until the critical word becomes available.
The pipeline resumes execution while the remaining words are being written to the cache.
Both caches are vi...


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