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MIPS32M4K

MIPS Technologies
Part Number MIPS32M4K
Manufacturer MIPS Technologies
Description Processor Core
Published May 4, 2006
Detailed Description ( DataSheet : www.DataSheet4U.com ) MIPS32™ M4K™ Processor Core Datasheet January 8, 2003 The MIPS32™ M4K™ core from ...
Datasheet PDF File MIPS32M4K PDF File

MIPS32M4K
MIPS32M4K

Overview
( DataSheet : www.
DataSheet4U.
com ) MIPS32™ M4K™ Processor Core Datasheet January 8, 2003 The MIPS32™ M4K™ core from MIPS® Technologies is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications.
The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor.
It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products.
The M4K core is ideally positioned to support new products for emerging segments of the routing, network access, network storage, residential gateway, and smart mobile device markets.
It is especially well-suited for applications requiring multiple cores, or even a single core, when high performance density is critical.
The M4K core implements the MIPS32 Release 2 Architecture with the MIPS16e™ ASE, and the 32-bit privileged resource architecture.
The Memory Management Unit (MMU) consists of a simple, Fixed Mapping Translation (FMT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer- (TLB) based MMU.
The synthesizable M4K core includes two different Multiply/Divide Unit (MDU) implementations, selectable at build-time, allowing the implementor to trade off performance and area.
The high-performance MDU option implements single cycle MAC instructions, which enable DSP algorithms to be performed efficiently.
It allows 32bit x 16-bit MAC instructions to be issued every cycle, while a 32-bit x 32-bit MAC instruction can be issued every 2 cycles.
The area-efficient MDU option handles multiplies with a one-bit-per-clock iterative algorithm.
The M4K core is cacheless; in lieu of caches, it includes a simple interface to SRAM-style devices.
This interface may be configured for independent instruction and data dev...


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