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MC100EP195

ON Semiconductor
Part Number MC100EP195
Manufacturer ON Semiconductor
Description 3.3V ECL Programmable Delay Chip
Published Apr 26, 2006
Detailed Description 3.3 V ECL Programmable Delay Chip MC100EP195 The MC100EP195 is a Programmable Delay Chip (PDC) designed primarily for...
Datasheet PDF File MC100EP195 PDF File

MC100EP195
MC100EP195

Overview
3.
3 V ECL Programmable Delay Chip MC100EP195 The MC100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment.
It provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and www.
onsemi.
com multiplexers as shown in the logic diagram, Figure 3.
The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.
2 ns.
The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10).
A LOW level on LEN allows a transparent LOAD mode of 1 32 real time delay values by D[9:0].
A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent LQFP−32 FA SUFFIX QFN32 MN SUFFIX changes in D[10:0].
The approximate delay values for varying tap CASE 561AB CASE 488AM numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Fig...


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