CLA90000 Datasheet

CLA90000 High Density CMOS Gate Arrays

( DataSheet : www.DataSheet4U.com ) CLA90000 Series High Density CMOS Gate Arrays DS5500 ISSUE 2.0 April 1997 INTRODUCTZarlinkION The CLA90000 family of gate arrays from Zarlink Semiconductor consists of 14 fixed-size arrays with the option of building optimized arrays with up to 1.1 million gat.

Features

I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for QuickSim II and Verilog-XL I CAD libraries optimized for synthesis I Up to 512K available gates and 352 pads with fixed arrays I Up to 1.1M available gates and 520 pads with optimized arrays I Double or triple layer metal on a 0.6µm (drawn) process I Operation from 2.7V to 5.5V I Methodologies for low c.