DatasheetsPDF.com

MB84VD2218xEH

Fujitsu Media Devices
Part Number MB84VD2218xEH
Manufacturer Fujitsu Media Devices
Description (MB84VD2218xEG/EH / MB84VD2219xEG/EH) 32M (x 8/x16) FLASH MEMORY & 4M (x 8/x16) STATIC RAM
Published Apr 12, 2006
Detailed Description ( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50206-1E Stacked MCP (Multi-Chip Package) F...
Datasheet PDF File MB84VD2218xEH PDF File

MB84VD2218xEH
MB84VD2218xEH

Overview
( DataSheet : www.
DataSheet4U.
com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50206-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 32M (× 8/×16) FLASH MEMORY & 4M (× 8/×16) STATIC RAM MB84VD2218XEG-90/MB84VD2219XEG-90 MB84VD2218XEH-90/MB84VD2219XEH-90 s FEATURES • Power supply voltage of 2.
7 V to 3.
3 V • High performance 90 ns maximum access time (Flash) 85 ns maximum access time (SRAM) • Operating Temperature –25°C to +85°C • Package 71-ball BGA (Continued) s PRODUCT LINE UP Flash Memory Ordering Part No.
VCCf,VCCs = 3.
0 V +0.
3 V –0.
3 V SRAM MB84VD2218XEG/EH-90/MB84VD2219XEG/EH-90 90 90 40 85 85 45 Max.
Address Access Time (ns) Max.
CE Access Time (ns) Max.
OE Access Time (ns) s PACKAGE 71-ball plastic FBGA (BGA-71P-M02) www.
DataSheet4U.
com www.
DataSheet4U.
com MB84VD2218XEG/EH/2219XEG/EH-90 (Continued) 1.
FLASH MEMORY • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Minimum 100,000 write/erase cycles • Sector erase architecture Eight 4 K words and sixty three 32 K words.
Any combination of sectors can be concurrently erased.
Also supports full chip erase.
• Boot Code Sector Architecture MB84VD2218X: Top sector MB84VD2219X: Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode.
• Low VCCf write inhibit ≤ 2.
5 V • Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a ne...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)