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DP83847

DsPHYTER II - Single 10/100 Ethernet Transceiver - National Semiconductor

DP83847 PDF File

Description

DP83847 DsPHYTER II — Single 10/100 Ethernet Transceiver February 2002 DP83847 DsPHYTER II — Single 10/100 Ethernet Transceiver General Description Features The DP83847 is a full feature single Physical Layer device s Low-power 3.
3V, 0.
18µm CMOS technology with integrated PMD sublayers to support both 10BASE-T s Power consumption < 351mW (typical) and 100BASE-TX Ethernet protocols over Category 3 (10 s 5V tolerant I/Os Mb/s) or Category 5 unshielded twisted pair cables.
s 5V/3.
3V MAC interface The DP83847 is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions.
It interfaces s IEEE 802.
3 ENDEC, 10BASE-T transceivers and filters to Twisted Pair media via an external transformer.
This s IEEE 802.
3u PCS, 100BASE-TX transceivers and filters device interfaces directly to MAC devices through the IEEE s IEEE 802.
3 compliant Auto-Negotiation 802.
3u standard Media Independent Interface (MII) ensuring interoperability between products from different ven- s Output edge rate control eliminates external filtering for Transmit outputs dors.
s BaseLine Wander compensation The DP83847 utilizes on chip Digital Signal Processing (DSP) technology and digital Phase Lock Loops (PLLs) for s IEEE 802.
3u MII (16 pins/port) robust performance under all operating conditions, s LED support (Link, Rx, Tx, Duplex, Speed, Collision) enhanced noise immunity, and lower external component s Single register access for complete PHY status count when compared to analog solutions.
s 10/100 Mb/s packet loopback BIST (Built in Self Test) s 56-pin LLP package (9w) x (9l) x (.
75h) mm Applications s LAN on Motherboard s Embedded Applications System Diagram Magnetics DP83847 Ethernet MAC MII 10/100 Mb/s DsPHYTER II RJ-45 10BASE-T or 100BASE-TX 25 MHz Clock Status LEDs Typical DsPHYTER II application ©2002 National Semiconductor Corporation www.
national.
com DP83847 MII HARDWARE CONFIGURATION PINS (AN_EN, AN0, AN1) (PAUSE_EN) (LED_CFG, PHYAD) SERIAL MANAGEMENT MDIO M...

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