DatasheetsPDF.com

PLL601-15

Part Number	PLL601-15
Manufacturer	PhaseLink
Description	Low Phase Noise PLL Clock Multiplier
Published	Feb 10, 2006
Detailed Description	m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 20-30MHz crystal ...
Datasheet	PLL601-15 PDF File

Overview

m o .
c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels.
t 20-30MHz crystal or clock.
• Reference a • Integrated crystal load capacitor: no external .
D load capacitor required.
w • Output clocks up to 150MHz at 3.
3V.
w • Low phase noise (-126dBc/Hz @ 1kHz).
w• Output Enable function.
• • • • Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION XIN GND GND GND 1 2 3 4 8 7 6 5 XOUT VDD VDD CLK Low jitter (RMS): 6.
4ps (period), 9.
4ps (accum.
) Advanced low power sub-micron CMOS process.
3.
3V operation.
Available in 8-Pin SOIC or TSSOP.
DESCRIPTIONS The PLL601-15 is a low cost, high performance and low phase noise clock synthesizer.
It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques for a fixed 5x multiplier.
The chip accepts crystal or clock inputs ranging from 20 to 30MHz, and produces outputs clocks up to 150MHz at 3.
3V.
BLOCK DIAGRAM XIN XOUT m o .
c U 4 t e e h S a t a .
D w w w CRYSTAL RANGE Multiplier 5x Xtal range 20-30MHz Phase Locked Loop PLL601-15 CLK XTAL OSC 47745 Fremont Blvd.
, Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 m o .
c 4U t e e h S a t a D .
w w w Rev 01/08/02 Page 1 Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PIN DESCRIPTIONS Name CLK VDD XIN XOUT GND Number 5 7,6 1 8 2, 3,4 Type O P I O P 3.
3V Power Supply.
Description Clock output from VCO.
Equals the input frequency times multiplier.
Crystal input to be connected to 20-30MHz fundamental parallel mode crystal (C L =15pF).
On chip load capacitors: No external capacitor required.
Crystal Connection.
Ground.
47745 Fremont Blvd.
, Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/08/02 Page 2 Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier ELECTRICAL SPECIFICATIONS 1.
Absolute Maximum Ratings PARAMETERS Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature A...

Similar Datasheet

PLL601-01 Low Phase Noise PLL Clock Multiplier - PhaseLink
PLL601-02 Low Phase Noise PLL Clock Multiplier - PhaseLink
PLL601-12 Dual Output PLL Clock - PhaseLink
PLL601-15 Low Phase Noise PLL Clock Multiplier - PhaseLink

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)