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PLL601-12

Part Number	PLL601-12
Manufacturer	PhaseLink
Description	Dual Output PLL Clock
Published	Feb 10, 2006
Detailed Description	m Preliminary PLL601-12 o c . Output PLL Clock with Selectable Odd Multiplier Dual U t4 FEATURES e PIN CONFIGURATION e (...
Datasheet	PLL601-12 PDF File

Overview

m Preliminary PLL601-12 o c .
Output PLL Clock with Selectable Odd Multiplier Dual U t4 FEATURES e PIN CONFIGURATION e (Top View) h • Selectable multipliers (x2.
5, x2.
75, x3, x4.
25, x5, x5.
5, x5.
75, S x6, x6.
25, x10, x11, x11.
5, x12, a x12.
5).
t • Crystala range from 13MHz to 31MHz (see SelecD tion Table for detailed acceptable input ranges).
.
• w Maximum output frequency: 312.
5MHz •w 2 CMOS outputs.
w• Selectable output drive (Standard or High-Drive).
VDD 1 2 3 4 5 6 7 14 13 12 11 10 9 8 S0^ S1^ PLL 601-12 XIN XOUT S3^ S2^ REF_SEL^ CLK2/ REF_CLK VDD • • • Selectable REF_CLK output.
3.
3V operation.
Available in 14-Pin SOP.
DESCRIPTIONS The PLL601-12 is a highly flexible XO with sele...

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