m 1Gb: x4, x8, x16 DDR SDRAM o Features c . U 4 t Double Data Rate (DDR) SDRAM e e– 64 Meg x 4 x 4 banks MT46V256M4 h S – 32 Meg x 8 x 4 banks MT46V128M8 a MT46V64M16 at – 16 Meg x 16 x 4 banks . D w w Features Options Marking w
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• VDD = +2. 5V ±0. 2V, VDDQ = +2. 5V ±0. 2V VDD = VDDQ = +2. 6V ±0. 1V (DDR400) • Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two –one per byte) • Programmable burst lengths: 2, 4, or 8 • Auto Refresh and Self Refresh Modes • Longer lead TSOP for improved reliability (OCPL) • 2. 5V I/O (SSTL_2 compatible) • Concurrent auto precharge option is supported • tRAS lockout supported (tRAP = tRCD) Table 1: Addressing Configuration
Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
m o . c U 4 t e e h S a t a . D w w w
• Configuration 256 Meg x 4 (64 Meg x 4 x 4 banks) 128 Meg x 8 (32 Meg x 8 x 4 banks) 64 Meg x 16 (16 Meg x 16 x 4 banks)1 • Plastic Package – OCPL 66-pin TSOP(400 mil width, 0. 65mm pin pitch) 66-pin TSOP lead-free (400 mil width, 0. 65mm pin pitch) • Timing – Cycle Time 7. 5ns @ CL = 2. 5 (DDR266B)2 6ns @ CL = 2. 5 (DDR333B)2 5ns @ CL = 3 (DDR400B) • Temperature Rating Commercial (0°C to +70°C) • Design Revision
256 Meg x 4 128 Meg x 8 64 Meg x 4 x 4 banks 8K 16K (A0–A13) 4(BA0,BA1) 4K(A0–A9, A11, A12) 32 Meg x 8 x 4 banks 8K 16K (A0–A13) 4(BA0,BA1) 2K(A0–A9, A11) Clock Rate CL = 2 100 MHz 133 MHz 133 MHz CL = 2. 5 133 MHz 167 MHz 167 MHz CL = 3 NA...
MT46V64M16 PDF File
